This invention is related to scan testing of complex digital circuits including integrated circuits (ICs), higher level assemblies and systems using ICs, and more particularly, to a method and apparatus for expanding test patterns applied to a restricted number of product primary inputs to inputs of a larger number of on-product scan chains for the purpose of scan testing.
Scan testing of digital circuits, internal sequential or register elements, such as latches, and the like, scattered between combinatorial components are designed in a way that they can be connected to each other in several parallel shift registers called scan chains. The inputs of the scan chains are connected to primary inputs (PIs) of the product under test. Each scan test typically requires that the scan chains be completely loaded with new test data one or more times using a scan load-operation. This loading operation takes place prior to applying a test sequence that exercises the logic connected to the register elements. The scan chains are loaded by repeatedly supplying a binary input data word with one bit of information for each scan chain followed by the application of one scan clock cycle. In response to the scan clock cycle, information already in the scan chains is shifted by one bit position towards the end of each chain. At the same time, the new information bit supplied at each scan chain input is loaded into the respective register element closest to each scan chain input. The number of scan clock cycles and input data words needed for completely loading all the scan chains is, thus, determined by the number of register elements in the longest scan chain.
The scan chains operate as clocked serial shift registers that are serially loaded with test input data (test stimulus data) from a suitable test stimulus data source. The procedure used for loading the scan chains is referred to as a scan-load operation. Automatic Test Equipment (ATE) is the most prevalent source of test stimulus data used for testing integrated circuits (IC) chips and higher-level assemblies. Once the test stimulus data has been loaded into the scan chains, the circuit under test can be exercised. These, in turn, result in certain test responses that are captured by the internal register elements that form the scan chains. The captured responses are, then, serially unloaded to a suitable test response sink for comparison with expected responses. ATE is one of such test response sinks. The procedure used for unloading is referred to as a scan-unload operation Data to be loaded is stored in the ATE and transferred to the component under test by shifting the scan chains. The total number of register elements in the component under test determines the amount of data needed for one complete load. The length of the longest scan chain and the shift cycle time determine the time needed for a complete load.
In order to reduce test time, it is advantageous to implement a large number of shorter scan chains rather than a small number of long chains. It should be noted that the use of more scan chains does not reduce by itself the total number of register elements and, hence, does not reduce the amount of data needed for a complete load. Furthermore, some scan tests may require more than one complete load to achieve fault detection. Hence, the total number of loads may exceed the number of tests in the full test program that must be applied to achieve the desired test coverage.
The number of register elements in modern ICs can exceed several hundred thousands. Thousands of scan tests-must be applied to achieve a good test coverage. In aggregate, the total amount of test data needed for a full test program begins to reach the limits of buffer storage available on a typical ATE used for a manufacturing test, even if the ATE is equipped with a dedicated scan buffer memory. Furthermore, typical ATEs often limit the maximum number of scan chains and the shift cycle rate. The fixed width and bandwidth of the scan interface result in longer scan chains and increased test time as the complexity of ICs grows with every new technology generation.
In conventional scan testing, test stimulus data is stored in ready-to-apply form in a high-speed buffer memory within the ATE and is directly loaded into the scan chains without additional data transformations. ATE architectures typically constrain the maximum of amount scan buffer memory available for scan test stimulus data, the maximum number of scan chains that can be serviced in parallel from a scan buffer memory, and the maximum cycle rate at which the data can be loaded into the scan chains. In other words, an ATE is characterized by a limited scan buffer space and a fixed, narrow bandwidth for transferring scan test stimulus data from ATE to the circuit under test.
Experience teaches that the number of register elements in a digital network grows proportionally with the size of the network, and that the number of tests also increases with network size. Consequently, the total amount of test stimulus data tends to grow more than linearly with network size and continuously threatens to exceed the buffer memory of installed ATEs, as new technology generations are introduced. Moreover, the limited bandwidth of existing ATE results in increasingly longer test times due to the larger amount of test stimulus data that must be applied to larger networks. An added area of concern is the time required to retrieve test data from archival storage, transfer it to the ATE, and load the data into the scan buffer memory. Combined, these trends contribute to a continuous degradation of throughput and productivity of the installed ATE with every new technology generation. It, further, results in a higher test cost due to longer test times and/or the need to invest in additional expensive ATE to increase the capacity of the manufacturing test floor. Further discussion of this problem can be found in the following two related articles:
xe2x80x9cBit-Flipping BISTxe2x80x9d by Hans-Joachim Wunderlich and Gundolf Kiefer, published in ICCAD ""96, pp. 337-346, 1996; and
xe2x80x9cSynthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BISTxe2x80x9d, by N. A. Touba and E. J. McCluskey, published in 1995 International Test Conference, pp. 174-682.
In both articles, the relative sparseness of care-bits for synthesizing custom logic that modifies data streams generated by an LFSR as needed for reconstructing the correct care-bit values is exploited. The disadvantage of these approaches is that the resulting custom logic is different for each design and constitutes an additional, unpredictable hardware overhead.
The present invention is based on a test data encoding concept published at the 1991 European Test Conference by Bernd Koenemann, in an article entitled xe2x80x9cLFSR-Coded Test Patterns for Scan Designsxe2x80x9d, pp.237-242. Several extensions of this scheme were subsequently published in academia and industry, e.g., by N. Zacharia et al., xe2x80x9cTwo-Dimensional Test Data Decompressor for Multiple Scan Designsxe2x80x9d, 1996 International Test Conference, pp. 186-194; and by Pieter M. Trouborst, xe2x80x9cLFSR Reseeding as a Component of Board Level Testxe2x80x9d, 1996 International Test Conference, pp. 58-96.
In all prior approaches, a Linear Feedback Shift Register (LFSR) within the IC under test is used as a means for test data expansion. The disadvantage of these approaches is that the width of the on-chip LFSR determines how many seed bit values are available as independent variables for encoding each test. Hardware cost considerations limit a reasonable width of the LFSR, which in turn limits the number of care bits that can be successfully encoded in each test. The methods are also sub-optimal from a semiconductor manufacturing test point of view in that they do not exploit the available bandwidth of the ATE. The ATE loads a seed into the LFSR at the beginning of each test but, then, essentially sits idle for many scan clock cycles until the test has been expanded and shifted into the internal scan chains inside the IC under test.
Attempts have been made to store and generate macros for built-in test pattern generation to improve the number of independent variables that can be loaded into the IC under test by suggesting how denser RAM/ROM structures can be used for variable storage in conjunction with traditional LFSRs. This approach, however, still requires that the encoded data be first downloaded into the circuit under test and then expanded internally while the expensive ATE sits idle, clearly a serious drawback.
Only recently, new methods have appeared wherein the independent variable data can be provided to an on-chip decoder from the ATE in real-time. One of such approaches is described by Abjhijit Jas et al., xe2x80x9cScan Vector Compression/Decompression Using Statistical Codesxe2x80x9d, VTS""99, pp. 114-120, 1999, which uses statistical coding techniques that are much more complex than the linear Boolean codes, which is much simpler to use and to implement and which is the subject of the present invention.
Thus, it is an object of the invention to provide a low-cost test pattern decoding means that can be cost-efficiently integrated into each IC under test.
It is another object of the invention to use a design-independent low-cost decoding network that exploits the existing ATE buffer memory rather than on-chip hardware to control the care-bit value generation.
It is still another object of the invention to establish a simple test pattern encoding scheme that permits preparing test data in a properly encoded form that is compatible with the decoding means provided by the decoding network.
It is a further object of the invention to overcome the above stated limits of previous methodologies by allowing the ATE to continuously supply independent variable data while the internal scan chains are shifted.
The invention solves both, the total test data volume problem and the test time problem, by integrating a novel real-time test data decoder in each IC. Test data is stored on the ATE and delivered to the IC under test in a highly compact, encoded format that is expanded in real-time within the IC under test.
The proposed novel decoder circuitry consists of a particularly simple and small logic network that connects the narrow scan data interface of the ATE to a much larger number of internal scan chains inside the IC under test. For example, a decoder network with an amplification factor of 8 expands the 32-bit encoded data words from the ATE into 256-bit wide decoded data words that are shifted into 256 internal scan chains in parallel. The amount of encoded data supplied by the ATE to completely load the scan chains consequently is much smaller (e.g., up to a factor of 8) than the total number of register elements in the scan chains. Because the number of scan chains inside the IC can be made so much larger than the width of the ATE""s scan interface, it is possible to proportionally reduce the length of the longest scan chain. The net result is a commensurate reduction of test time (e.g., up to a factor of 8).
For the complete methodology, an equally simple encoding algorithm allows Automatic Test Pattern Generation (ATPG) software to organize the test data in appropriately encoded form for use with the proposed decoder hardware. The key contributing characteristic of automatically generated scan tests is that only a very small subset of register element data values needs to be at a specific xe2x80x9ccarexe2x80x9d value for any given test, while the vast majority of data values are xe2x80x9cdon""t caresxe2x80x9d. The proposed encoding algorithm exploits both, the sparseness of the xe2x80x9ccarexe2x80x9d values and the freedom to arbitrarily assign xe2x80x9cdon""t carexe2x80x9d values, to achieve a significant reduction in the encoded data without losing test coverage.
Despite being simple and requiring a uniquely small circuit overhead in the ICs under test, the disclosed method achieves a large reduction in ATE-resident test data volume and test time when compared to current practices of traditional scan test methods. Because the proposed decoding is performed on the IC under test, no special ATE hardware or software features are needed. The disclosed invention, thus, extends the useful lifetime, and vastly improves the productivity of lower-cost and existing ATE equipment. Since the ATE consumes a considerable portion of semiconductor manufacturing capital investment and operating costs, the invention has the potential of measurably improving the profitability of manufacturing semiconductor products.
In a first aspect of the invention, there is provided a method for testing logic products consisting of a plurality of internal scan chains wherein the number of the internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, the method including the steps of: a) inserting a combinatorial or sequential logic network between the primary inputs and the inputs of the scan chains, the logic network receiving input data words having a width corresponding to the number of primary inputs, the logic network further expanding the input data words into output data words having a width that corresponds to the number of the internal scan chains; b) constructing each input data word such that the values of a predetermined set of bits in each output data word exactly match predetermined values established for achieving improved test coverage; c) supplying a plurality of input data words to the primary inputs; d) from each such input data word, deriving one or several wider output data words; e) loading the bit values of each the wider output data word into register elements of the internal scan chains while data previously loaded into the scan chains is shifted forward inside the scan chains; and f) supplying as many of the input data words to the primary inputs to generate as many derived expanded data words to be loaded into the internal scan chains as needed to achieve an improved test coverage.
In a second aspect of the invention, there is provided an apparatus for testing logic products containing a plurality of internal scan chains wherein the number of the internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, the apparatus including: a) a combinatorial or sequential logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs converts the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values of each the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit position, wherein a first plurality of the input data words supplied to the primary inputs generates a second plurality of expanded data words that are loaded into the internal scan chains to achieve a predetermined test coverage.